1. Field of the Invention
The present invention generally relates to the field of fabricating integrated circuits, and, more particularly, to the formation of semiconductor devices including field effect transistors, such as MOS transistors, and passive capacitors having a reduced leakage current.
2. Description of the Related Art
In modem integrated circuits, a huge number of individual circuit elements, such as field effect transistors in the form of CMOS, NMOS, PMOS elements, resistors, capacitors, and the like, are formed on a single chip area. Typically, feature sizes of these circuit elements are steadily decreasing with the introduction of every new circuit generation, to provide currently available integrated circuits with an improved degree of performance in terms of speed and power consumption. A reduction in size of transistor is an important aspect in steadily improving device performance of complex integrated circuits, such as CPUs, as the reduction in size commonly brings about an increased switching speed, thereby enhancing signal processing performance and also power consumption, since, due to the reduced switching time period, the transient currents upon switching a CMOS transistor element from logic low to logic high are significantly reduced. On the other hand, the reduction of feature sizes, such as the channel length of the transistor elements in the deep sub-micron regime, entails a plurality of issues that may partially offset the advantages obtained by the improved switching performance. For example, reducing the channel length of field effect transistors requires the reduction of the thickness of the gate insulation layer in order to maintain a sufficiently high capacitive coupling of the gate electrode to the channel region so as to appropriately control the formation of the conductive channel upon application of a control voltage to the gate electrode. For highly sophisticated devices, currently featuring a channel length of 0.18 xcexcm or even less, typically comprising silicon dioxide for the superior and well known characteristics of the interface between the silicon dioxide and the underlying channel region, a thickness of the gate insulation layer is on the order of 2-5 nm or even less. For a gate dielectric of this order of magnitude, it turns out that, in total, the leakage current passing through the thin gate dielectric may become comparable to the transient currents, since the leakage currents exponentially rise as the gate dielectric thickness is linearly reduced.
In addition to the large number of transistor elements, plural passive capacitors are typically formed in integrated circuits that are used for a plurality of purposes, such as for de-coupling purposes. Since these capacitors are usually formed in and on active semiconductor regions, acting as a first capacitor electrode, with a dielectric layer having characteristics in conformity with process requirements for the concurrently fabricated field effect transistors, and a second capacitor electrode formed of the gate electrode material, the problem of leakage current is significantly exacerbated owing to the large chip area occupied by these capacitor elements. Consequently, the capacitors significantly contribute to the total gate leakage consumption and, therefore, to the total power consumption of the integrated circuit. For applications requiring a minimum power consumption, such as portable battery-powered devices, the high amount of static power consumption may not be acceptable, and, therefore, usually a so-called dual gate oxide processing may be used to increase the thickness of the dielectric layer of the capacitors, thereby reducing the leakage current of these elements.
With reference to FIGS. 1a-1c, a typical prior art process flow for forming capacitors having a reduced leakage current will now be described. FIG. 1a schematically shows a cross-sectional view of a semiconductor device 100 at an initial manufacturing stage. The semiconductor device 100 comprises a substrate 101, for example a silicon substrate, including a first active semiconductor region 120 and a second active semiconductor region 130, which are enclosed by respective isolation structures 102. The second active region 130 and the corresponding isolation structure 102 are covered by a mask layer 103 that may be comprised of photoresist. The first active region 120 comprises a surface portion 104 having severe lattice damage caused by an ion implantation, as indicated by 105.
A typical process flow for forming the semiconductor device as depicted in FIG. 1a includes sophisticated photolithography and etch techniques for defining the isolation structures 102 followed by a further photolithography step to pattern the resist mask 103. As these process techniques are well known in the art, a detailed description thereof is omitted. Subsequently, the ion implantation 105 is carried out with any appropriate ions, such as silicon, argon, xenon and the like, wherein a dose and energy is selected to create severe lattice damage in the portion 104, thereby significantly changing the diffusion behavior of the portion 104 during an oxidation process that is to be carried out subsequently.
FIG. 1b schematically shows the semiconductor structure 100 in an advanced manufacturing stage. A first dielectric layer 121, substantially comprised of silicon dioxide, and having a first thickness 122, is formed on the first active region 120. A second dielectric layer 131 having a second thickness 132 and comprised of the same material as the first dielectric layer 121 is formed on the second active region 130. The first and the second dielectric layers 121 and 131 are formed by conventional oxidation in a high temperature furnace process or by a rapid thermal oxidation process. Due to the severe lattice damage of the surface portion 104, the oxygen diffusion in this surface portion 104 is significantly enhanced compared to silicon portions having a substantially intact crystallinity, such as in the second active region 130. Consequently, oxide growth in and on the first active region 120 is increased compared to the growth rate of the second active region 130 so that the second thickness 132 differs from the first thickness 122 by approximately 0.2-1.0 nm for a thickness of the second dielectric layer 131 on the order of 1-5 nm.
FIG. 1c schematically shows the semiconductor device 100 in a further advanced manufacturing stage, wherein a capacitor 140 is formed in and on the first active region 120, and a field effect transistor 150 is formed in and on the second active region 130. The transistor element 150 comprises a gate electrode 133 including, for example, highly doped polysilicon and a metal silicide portion 135. Moreover, sidewall spacers 134 are formed adjacent to sidewalls of the gate electrode 133. Source and drain regions 136, each including a metal silicide portion 135, are formed in the second active region 130. The capacitor 140 comprises a conductive portion 123 comprised of the same material as the gate electrode 133 and is formed over the first dielectric layer 121. The portion 123 represents one electrode of the capacitor 140. The capacitor electrode 123 includes a metal silicide portion 125 and is enclosed by sidewall spacer elements 124.
A typical process flow for forming the transistor element 150 and the capacitor 140 may include the following steps. A polysilicon layer may be deposited over the device as shown in FIG. 1b and is patterned by well known photolithography and etching techniques to create the capacitor electrode 123 and the gate electrode 133. Subsequently, the drain and source region are formed by ion implantation, intermittently the sidewall spacers 134 and the sidewall spacers 124 are formed so that the sidewal spacers 134 may act as implantation masks to appropriately shape the dopant concentration of the drain and source regions 136. Thereafter, the metal silicide portions 125 and 135 are formed by depositing a refractory metal and initiating a chemical reaction between the metal and the underlying polysilicon of the capacitor electrode 133, and the silicon in the drain and source regions 136.
As is evident from FIG. 1c, the capacitor 140 having the first dielectric layer 121 with the increased thickness 122 will exhibit a significantly reduced leakage current rate compared to the corresponding leakage rate caused by the relatively thin second dielectric layer 131 having the second thickness 132 that is optimized to provide the required dynamic performance of the transistor 150. Although a remarkably improved leakage rate of the capacitor 140 may be obtained with the above-described conventional approach, one decisive drawback is the significantly reduced capacitance per unit area of the capacitor 140 owing to the increased thickness of the first dielectric layer 121. A further disadvantage of the conventional prior art approach is the requirement of a high temperature oxidation process for forming the first and second dielectric layers 121 and 131 so that this process scheme is not compatible with alternative solutions for forming extremely thin gate dielectrics, such as advanced deposition methods for forming ultra thin gate insulation layers. Moreover, the ion bombardment 105 for forming the surface portion 104 (FIG. 1a) may entail a significant oxide degradation and thus may give rise to reliability issues of the first dielectric layer 121, thereby causing premature device failure.
In view of the above-identified problems, there is a need for improved semiconductor devices including transistor elements and passive capacitors, in which leakage current of the capacitors is improved without unduly adversely affecting device characteristics, such as capacitance per unit area, and process compatibility during manufacturing of the device and/or reliability.
Generally, the present invention is directed to a semiconductor device and a corresponding manufacturing method, wherein a passive capacitor includes a dielectric exhibiting a relatively high permittivity so that the capacitance per unit area may significantly be increased while a thickness of the dielectric may be selected appropriately to ensure a low desired leakage rate. At the same time, the gate insulation layer of field effect transistors may be formed in accordance with process requirements and with a material that ensures the required performance of the transistor device. The present invention is, therefore, based on the inventors"" concept that although presently the employment of high-k materials for gate dielectrics in field effect transistors has not been successfully implemented, as these materials cause significant transistor degradation owing to the reduced channel mobility caused by these high-k materials, they may nevertheless be implemented into the same chip area as a capacitor dielectric, since the capacitor performance is not substantially affected by the deteriorated carrier mobility at the interface between the high-k dielectric and the underlying active region.
According to one illustrative embodiment of the present invention, a semiconductor device comprises a first active semiconductor region and a second active semiconductor region separated from each other by a dielectric isolation structure. A capacitor is formed in and over the first active semiconductor region with a first dielectric layer formed on the first active region, wherein the first dielectric layer has a first permittivity. Moreover, a field effect transistor is formed in and on the second active semiconductor region, wherein the field effect transistor includes a gate insulation layer comprising a material having a second permittivity that is less than the first permittivity.
According to yet another illustrative embodiment of the present invention, a semiconductor device comprises a first capacitive element formed in and on a first semiconductor region and a second capacitive element formed in and on a second active region. The first and the second capacitive elements comprise, respectively, a first dielectric layer having a first thickness and a second dielectric layer having a second thickness, and a first conductive layer formed on the first dielectric layer and a second conductive layer formed on the second dielectric layer. Additionally, a capacitance per unit area of the first capacitive element is equal or higher than that of the second capacitive element, wherein the second thickness is less than the first thickness.
According to still another illustrative embodiment of the present invention, a method of forming a semiconductor device comprises providing a substrate having formed thereon a first semiconductor region and a second semiconductor region separated by an isolation structure. Moreover, a first dielectric layer having a first permittivity and a first thickness is formed on the first semiconductor region. Additionally, a second dielectric layer having a second permittivity and a second thickness is formed on the second semiconductor region. Additionally, a conductive material is formed on the first and the second dielectric layers to create a first and a second capacitive element, wherein the first permittivity is higher than the second permittivity.
In accordance with yet a further illustrative embodiment of the present invention, a method of fabricating a semiconductor device including a field effect transistor element and a passive capacitor comprises defining a first active region and a second active region by forming shallow trench isolations. Furthermore, a first dielectric layer is formed on the first semiconductor region as a capacitor dielectric and a second dielectric layer is formed on the second active region as a gate insulation layer of the field effect transistor element. Moreover, a permittivity of the first dielectric layer is higher than that of the second dielectric layer.